The TSPI ASIC
team fully understands a client's need for a reliable partner in providing suitable, cost-effective solutions to circuit integration design issues. That's why we have a cache of world-class expertise ready to acknowledge the client's every request. Dynamic and flexible, the client's satisfaction is the number one priority, a non-maskable interrupt. Our FIFO of expertise is an array of design solutions involving a range of circuit configurations. We are committed to deliver in burst mode, with parity checking, anytime, anywhere and with a smile.
The TSPI ASIC
team’s capability spans the full range of design, implementation, test vector creation, simulation, synthesis, gate simulation, static analysis, back annotation up to the evaluation of the engineering sample and the system board. The team is not only well versed both in Verilog and VHDL, but they are also capable of C and assembly language programming, a skill necessary for evaluating their own designs. And once debugging gets really tough, you can depend on them to roll up their sleeves, figure out the maze of jump tags in the circuit diagram and do their own soldering and wiring to verify timing and signals, the undershoot and overshoot, utilizing the logic analyzer and/or the oscilloscope.
Well-proven design methodologies, internal proprietary tools to speed-up design implementation and testing, easy-to-synthesize and reusable codes, use of behavioral models for testing, focus on client requirements, ability to learn and adapt, individual skills, right attitude and team effort combine for a potent force, which is the ASIC design team.
Success Stories
Printer Controller ASIC Applications
 1.
Project Name: Multi-Function 600 DPI 62-PPM Laser Printer Controller
Project Abstract:
This is a Multi-CPU LASER Printer Controller.
The multi-CPU architecture, which allows the
printer to execute print jobs in parallel, enables
it to achieve a maximum print speed of 62-Pages
Per Minute. The secret of it all is in the TSPI-designed
115K gate ASIC mounted on each of the boards. The
2-mode, master & slave ASIC, includes a
proprietary bus protocol, allowing the
communication and transfer of data among the 4
CPUs. The ASIC also features a system arbiter,
memory arbiters, and controller for SDRAM, SRAM,
NOVRAM, IDE hard disk, SCSI devices, CPU, laser
printer engine and LCD panel display.
Development Language and
Tools:
• Verilog Hardware Design Language
• IDT4650 Assembly and C Language
• Simulator: ModelSim, Verilog-XL
• Synthesis Tool: Synopsys Design Compiler,
Galileo
• Place and Route Tool: Altera Maxplus
• Static Analysis: NEC Tiara
• NEC Proprietary Development Tool: Open
CAD
• Logic Analyzer and Oscilloscope
Software Platform:
• Solaris, Windows NT
Hardware Platform:
• Sunsparc, Windows-based PC
2.
Project Name: 600 DPI 20 PPM Laser Printer Scanner
and Copier Controller
Project Abstract:
This is an image processor with scanner and printer interface. This 600K gate ASIC was designed using Verilog. Aside from having both a USB and IEEE1284 host interface, this ASIC features a memory controller and interface arbiter designed for simultaneous flow of data from different sources and destinations seamlessly without collision.
Development Language and Tools:
• Verilog Hardware Design Language
• Simulator: ModelSim, Verilog-XL
• Synthesis Tool: Synopsys Design Compiler,
Leonardo Spectrum
• Static Analysis: Synopsys Prime Time
• NEC Proprietary Development Tool: OpenCAD
Software Platform:
• Solaris, Windows NT
Hardware Platform:
• Sunsparc, Windows-based PC
IP Cores
3.
Project Name: USB 1.1 Controller
Project Abstract:
This
is a customized USB Controller that specifically supports Printer and Scanner
Class Devices. It is USB1.1 compliant, capable of transferring data 12 mega
bits per second at full speed. Complete with Serial Interface Engine, Protocol
Layer and Device Specific Inter.
Development Language and
Tools:
• Verilog Hardware Design Language
• Simulator: ModelSim, Verilog-XL
• Synthesis Tool: Synopsys Design Compiler,
Leonardo Spectrum, Synplify
• Place and Route Tool: Altera QuartusII
• Static Analysis: Synopsys Prime Time
• Logic Analyzer and Oscilloscope
Software Platform:
• Solaris, Windows NT
Hardware Platform:
• Sunsparc, Windows-based PC
4.
Project Name: USB 2.0 Controller
Project Abstract:
This USB Controller was designed to support any type of device classes. This is achieved by the programmability applied in endpoint numbers and endpoint types. Designed to be UTMI and USB 2.0 compliant, this USB controller is capable of both high speed and full speed. This means that it can transfer data at a rate of 12 or 480 mega bits per seconds. It can accommodate a Wishbone Compliant CPU and DMA interfaces for the device side. Verilog Hardware Definition Language was used to design this IP Core.
Development Language and
Tools:
• Verilog Hardware Design Language
• Simulator: ModelSim
• Synthesis Tool: Synopsys Design Compiler,
Leonardo Spectrum, Synplify
• Place and Route Tool: Altera Quartus II
• Static Analysis: Synopsys Prime Time
• Logic Analyzer and Oscilloscope
Software Platform:
• Windows NT
Hardware Platform:
• Windows-based PC
5.
Project Name: Serial ATA Controller
Project Abstract:
The serial ATA controller supports first generation
S-ATA standards. It is capable of transferring data at the rate of one hundred
and fifty megabytes per second. It is connected to the host ASIC by ATAPI-6
interface and an optional Wishbone compliant CPU interface. ATAPI-6 interface
support eases migration to the S-ATA standard.
Development Language and Tools:
• Verilog Hardware Design Language
• Simulator: ModelSim
• Synthesis Tool: Synopsys Design Compiler,
Leonardo Spectrum, Synplify
• Place and Route Tool: Altera QuartusII
• Static Analysis: Synopsys Prime Time
• Logic Analyzer and Oscilloscope
Software Platform:
• Windows NT
Hardware Platform:
• Windows-based PC
Communications
6.
Project Name: Communications Equipment Applications
Project Abstract:
This is an FPGA chip controller of a data exchange system of an IP switch router of an established Japanese OEM company. This 278K-gate controller was developed using 12K lines of VHDL code and tested using 24K lines of test bench code for 3 months by 3 engineers.
Development Language and
Tools:
• VHDL
• Simulator: ModelSim
• Synthesis Tool: Xilinx Foundation Series
• Place and Route Tool: Xilinx Foundation
Series
Software Platform:
• Windows NT
Hardware Platform:
• Windows-based PC
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